SH7785 Datasheet, PDF (377/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Section 11 Local Bus State Controller (LBSC)
The local bus state controller (LBSC) divides the external memory space and outputs control
signals according to the specification of each memory and bus interface. The LBSC function
enables connection of the SRAM or ROM, etc. to this LSI. The LBSC also supports the PCMCIA
interface protocol, which implements simple system design and high-speed data transfers in a
compact system.
11.1 Features
The LBSC has the following features.
• Manages areas 0 to 6 of the external memory space divided into seven
⎯ Maximum 64 Mbytes for each of areas 0 to 6
⎯ Bus width of each area can be set by a register (Only the area-0 bus width is set by an
external pin.)
⎯ Wait cycle insertion by the RDY pin
⎯ Wait cycle insertion can be controlled by a program
⎯ Type of memory to be connected is specifiable for each area
⎯ Control signals are output for memory connected to each area
⎯ Automatic wait cycle insertion to prevent data bus collision in consecutive memory
accesses
⎯ The write strobe setup and hold time periods can be inserted in a write cycle to connect to
low-speed memory
• SRAM interface
⎯ Wait cycle insertion can be controlled by a program
Connectable area: 0 to 6
Settable bus width: 64, 32, 16 and 8 bits
• Burst ROM interface
⎯ Wait cycle insertion can be controlled by a program
⎯ Burst transfers for the number of times specified by the register
Connectable area: 0 to 6
Settable bus width: 64, 32, 16 and 8 bits
Rev.1.00 Jan. 10, 2008 Page 347 of 1658
REJ09B0261-0100