SH7785 Datasheet, PDF (1021/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
2. Setting Method When Setting Values in Succession
When setting values in this register in succession, the CL module is able to receive the
next command while the CL_CFF bit in CLSR is 0. To perform processing by changing
the command alone, just set the new command in this register.
3. The input Y/U/V pointers and output pointers must be set to point to addresses on 32-
byte boundaries. If not, the lower address is regarded as 0.
4. Two commands can be received. If the next command is written when the command
FIFO is full, the commands stored in the command FIFO are retained and the next
command is ignored.
20.3.13 CL Control Register (CLCR)
CLCR is in the CL register block and specifies the CL operating mode.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
⎯⎯⎯⎯⎯⎯⎯
7
6
5
CL_DA
4
3
2
1
0
⎯ CL_OD CL_OA CL_MD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W ⎯ R/W R/W R/W
Bit
Bit Name
31 to 9 ⎯
8 to 4 CL_DA
3
⎯
2
CL_OD
Initial
Value R/W
All 0 ⎯
All 0 R/W
0
⎯
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies output data alignment.
The correspondence between the alignment and
specified value is shown in the following table.
Reserved
This bit is always read as 0. The write value should
always be 0.
Specifies output access size (access size for output)
0: 4 bytes
1: 32 bytes
Rev.1.00 Jan. 10, 2008 Page 991 of 1658
REJ09B0261-0100