SH7785 Datasheet, PDF (794/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.3.2 Watchdog Timer Control/Status Register (WDTCSR)
WDTCSR is a 32-bit readable/writable register comprising timer mode-selecting bits and overflow
flags.
WDTCSR should be written to as a longword unit, with H'A5 in the most significant byte. The
value read from this byte is always H'00. WDTCSR is only rest by a power-on reset caused by the
PRESET pin.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Code for writing (H'A5)
⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TME WT/IT RSTS WOVF IOVF ⎯ ⎯ ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R R R
Initial
Bit
Bit Name Value R/W
31 to 24 (Code for All 0 R/W
writing)
23 to 8 ⎯
All 0 R
7
TME
0
R/W
6
WT/IT
0
R/W
Description
Code for writing (H'A5)
These bits are always read as H'00. When writing to
this register, the value written to these bits must be
H'A5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Enable
Starts or stops the timer operation.
0: Stops counting up.
1: Starts counting up.
Timer Mode Select
Specifies whether the WDT is used as a watchdog
timer or interval timer. Up counting may not be
performed correctly if this bit is modified while the
WDT is running.
0: Interval timer mode
1: Watchdog timer mode
Rev.1.00 Jan. 10, 2008 Page 764 of 1658
REJ09B0261-0100