SH7785 Datasheet, PDF (518/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
12.4.5 SDRAM Timing Register 0 (DBTR0)
The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon
power-on reset.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯ ⎯ ⎯ ⎯ ⎯ CL2 CL1 CL0 ⎯ ⎯ ⎯ ⎯ TRAS3 TRAS2 TRAS1 TRAS0
Initial value: 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
R/W: R R R R R R/W R/W R/W R R R R R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ TRFC6 TRFC5 TRFC4 TRFC3 TRFC2 TRFC1 TRFC0 ⎯ ⎯ ⎯ ⎯ ⎯ TRCD2 TRCD1 TRCD0
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
R/W: R R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W
Bit
Bit Name
31 to 27 ⎯
Initial
Value
All 0
26 to 24 CL2 to CL0 010
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W CAS Latency Setting Bits
These bits set the CAS latency. These bits should be
set according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
When using the ODT (On Die Termination) enable
output signal MODT, these bits should be set to 4 or
more cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
010: 2 cycles
011: 3 cycles
100: 4 cycles
101: 5 cycles
110: 6 cycles
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
Rev.1.00 Jan. 10, 2008 Page 488 of 1658
REJ09B0261-0100