SH7785 Datasheet, PDF (871/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.1 Display Unit System Control Register
The display unit system control register (DSYSR) sets the system operation for the display unit
(DU).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — DSEC — — — IUPD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R R R/W
Internal update:
O
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — DRES DEN
TVM
SCM
————
Initial value: 0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R R R R
Internal update:
O
Bit
Bit Name
31 to 21 ⎯
Initial
Value
All 0
20
DSEC
0
19 to 17 ⎯
All 0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Yes
Display Data Endian Conversion
For details of data swap, see section 19.4.7,
Endian Conversion.
0: Display data in memory is not byte-data/word-
data swapped
1: Display data in memory is byte-data/word-
data swapped
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 841 of 1658
REJ09B0261-0100