SH7785 Datasheet, PDF (875/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.2 Display Mode Register (DSMR)
The display mode register (DSMR) sets the display operation of the display unit.
Bit: 31 30 29 28 27 26 25 24 23 22 21
— — — VSPM ODPM
DIPM
CSPM — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R
Internal update:
*
*
*
*
*
Bit: 15 14 13 12 11 10 9
8
7
6
5
CDEL
CDEM
CDED —
—
— ODEV
CSY
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R/W R/W R/W R
Internal update: *
*
*
*
*
20 19 18 17 16
— DIL VSL HSL DDIS
0
0
0
0
0
R R/W R/W R/W R/W
*
*
*
*
4
3
2
1
0
—————
0
0
0
0
0
RRRRR
Bit
Bit Name
31 to 29 ⎯
Initial
Value
All 0
28
VSPM
0
27
ODPM 0
26, 25 DIPM
00
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W *
VSYNC Pin Mode
Settings in DSYSR are given priority over
settings in this register.
0: VSYNC signal is output to the VSYNC pin
1: CSYNC signal is output to the VSYNC pin
R/W *
ODDF Pin Mode
0: ODDF signal is output to the ODDF pin
1: CLAMP signal is output to the ODDF pin
The ODDF pin is an output pin even when the
TVM bit in DSYSR is set to TV sync mode.
R/W *
DISP Pin Mode
00: DISP signal is output to the DISP pin
01: CSYNC signal is output to the DISP pin
10: Setting prohibited
11: DE signal is output to the DISP pin
Rev.1.00 Jan. 10, 2008 Page 845 of 1658
REJ09B0261-0100