SH7785 Datasheet, PDF (670/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
13.4.4 Target Access
This section describes how the PCIC in this LSI is accessed by an external PCI local bus master
when the PCIC is used in both the host mode and normal mode.
(1) Accessing Memory Space in This LSI
Accesses to the PCIC in this LSI by an external PCI bus master are described below.
PCI bus address space (4GB)
H'00000000 _{Memory base 0}
Memory base 1
SHwy bus address space (4GB)
H'00000000
Local address
space 0 (base 0)
Local address
space 1 (base 1)
H'FFFFFFFF
PCI I/O space
I/O space
H'FE000000
H'FE3FFFFF
H'FFFFFFFF
I/O base
Figure 13.10 Memory Map from PCI Bus to SuperHyway Bus
Rev.1.00 Jan. 10, 2008 Page 640 of 1658
REJ09B0261-0100