SH7785 Datasheet, PDF (1635/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
32.3.10 H-UDI Module Signal Timing
Table 32.15 H-UDI Module Signal Timing
Conditions: V_DDQ= 3.0 to 3.6 V, V_DD= 1.1 V, T_a= −40 to 85°C, C_L= 30 pF, PLL2 on
Item
Symbol Min. Max. Unit Figure Remarks
Input clock cycle
t
50
—
ns 32.44,
TCKcyc
32.46
Input clock pulse width (high)
t_TCKH
15
—
ns 32.44
Input clock pulse width (low)
t
15
—
ns
TCKL
Input clock rise time
t
—
10
ns
TCKr
Input clock fall time
ASEBRK setup time
ASEBRK hold time
t
—
10
ns
TCKf
t
10
—
t
32.45
ASEBRKS
cyc
t
1
ASEBRKH
—
ms
TDI/TMS setup time
t_TDIS
15
—
ns 32.46
TDI/TMS hold time
t_TDIH
15
—
ns
TDO data delay time
t_TDO
0
12
ns
ASE-PINBRK pulse width
t_PINBRK
2
—
t_Pcyc 32.47
Notes: 1. During a boundary scan, t is the period corresponding to a frequency of 10 MHz, i.e.
TCKcyc
0.1 μs.
2. t_cyc is the period of one CKIO clock cycle.
3. t_Pcyc is the period of one peripheral clock (Pck) cycle.
1/2V_DDQ
t_TCKcyc
t_TCKH
t_TCKL
V_IH
VIH
V_IL
VIL
t_TCKf
V_IH
1/2V_DDQ
t_TCKr
Note: When the clock is input from the TCK pin.
Figure 32.44 TCK Input Timing
Rev.1.00 Jan. 10, 2008 Page 1605 of 1658
REJ09B0261-0100