SH7785 Datasheet, PDF (1377/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
Bit
25
24
23, 22
21
20
19, 18
17
Initial
Bit Name Value
CDSRC 0
DOSR
0
—
All 0
SELRW 0
DOADR 0
ADRCNT 00
[1:0]
DOCMD2 0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Data Buffer Specification
Specifies the data buffer to be read from or written to in
the data stage* in command access mode.
0: Specifies FLDATAR as the data buffer.
1: Specifies FLDTFIFO as the data buffer.
Status Read Check
Specifies whether the status read is performed after the
second command has been issued in command access
mode.
0: Performs no status read
1: Performs status read
Reserved
These bits are always read as 0. The write value should
always be 0.
Data Read/Write Specification
Specifies whether the direction is read or write in data
stage.
0: Read
1: Write
Address Stage Execution Specification
Specifies whether the address stage* is executed in
command access mode.
0: Performs no address stage
1: Performs address stage
Address Issue Byte Count Specification
Specify the number of bytes for the address data to be
issued in address stage*.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
Second Command Stage* Execution Specification
Specifies whether the second command stage* is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
Rev.1.00 Jan. 10, 2008 Page 1347 of 1658
REJ09B0261-0100