SH7785 Datasheet, PDF (1138/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
22.3.3 Transmit Data Register (SITDR)
SITDR is a 32-bit write-only register that specifies SIOF transmit data.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITDL[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: W W W W W W W W W W W W W W W W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SITDR[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name Value R/W
31 to 16 SITDL[15:0] Undefined W
15 to 0 SITDR[15:0] Undefined W
Description
Left-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as left-channel data. The position of the
left-channel data in the transmit frame depends on the
value set in the TDLA bit in SITDAR.
• These bits are valid when the TDLE bit in SITDAR is
set to 1.
Right-Channel Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as right-channel data. The position of
the right-channel data in the transmit frame depends on
the value set in the TDRA bit in SITDAR.
• These bits are valid when the TDRE bit in SITDAR
is set to 1, and the TLREP bit in SITDAR is cleared
to 0.
Rev.1.00 Jan. 10, 2008 Page 1108 of 1658
REJ09B0261-0100