SH7785 Datasheet, PDF (238/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
C. If the MT bit in IRMCR is set to 0 (initial value) before accessing the memory-mapped
PMB, no specific sequence is required.
However, correct operation with method C may no longer be guaranteed in future SuperH-
family products. Selection of step A or B is recommended to ensure compatibility with future
SuperH-family products.
(2) When the Program Modifying the PMB is in Areas Other than the P1 or P2 Area
1. Invalidate the entry remaining in the ITLB by writing 1 to the TI bit in MMUCR.
2. In the memory-mapped PMB, change PMB entries.
3. Execute one of the following steps, A, B, and C. Do not execute a branch or operand access for
the P1 or P2 area before this execution.
A. Perform a branch using the RTE instruction.
B. Execute the ICBI instruction for any address (including non-cacheable area).
C. If the MT bit in IRMCR is set to 0 (initial value) before accessing the memory-mapped
PMB, no specific sequence is required.
However, correct operation with method C may no longer be guaranteed in future SuperH-
family products. Selection of step A or B is recommended to ensure compatibility with future
SuperH-family products.
Rev.1.00 Jan. 10, 2008 Page 208 of 1658
REJ09B0261-0100