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| SH7785 Datasheet, PDF (1510/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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29. User Break Controller (UBC)
29.4 User Break Debugging Support Function
By using the user break debugging support function, the branch destination address can be
modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of
break control register CBCR to 1 allows branching to the address indicated by DBR instead of
branching to the address indicated by the [VBR + offset]. Figure 29.2 shows the flowchart of the
user break debugging support function.
Hardware operations
Exception/interrupt
is generated
SPC â PC
SSR â SR
SR.BL â B'1
SR.MD â B'1
SR.RB â B'1
Exception
EXPEVT â Exception code
Exception/interrupt/trap?
Interrupt
INTEVT â Interrupt code
Trap
EXPEVT â H'160
TRA â TRAPA (imm)
SGR â R15
No
Yes
Reset exception?
Yes
(CBCR.UBDE == 1)
No
&& (user break)?
PC â DBR
PC â VBR + vector offset
PC â H'A000 0000
Debugging program
R15 â SGR
(STC instruction)
Exception handling routine
Execute RTE instruction
PC â SPC
SR â SSR
Exception operation ends
Figure 29.2 Flowchart of User Break Debugging Support Function
Rev.1.00 Jan. 10, 2008 Page 1480 of 1658
REJ09B0261-0100
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