SH7785 Datasheet, PDF (511/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
Table 12.10 Register Status in each Processing Mode
Power-On Reset Manual Reset Sleep/Deep Sleep
Register Name Abbreviation
By PRESET pin/ By WDT/Multiple By SLEEP
WDT/H-UDI
Exception
Instruction
DBSC2 status
register
DBSTATE
H'0000 0x00*
Retained
Retained
SDRAM operation DBEN
enable register
H'0000 0000
Retained
Retained
SDRAM command DBCMDCNT
control register
H'0000 0000
Retained
Retained
SDRAM
configuration
setting register
DBCONF
H'009A 0001
Retained
Retained
SDRAM timing
register 0
DBTR0
H'0203 0501
Retained
Retained
SDRAM timing
register 1
DBTR1
H'0001 0001
Retained
Retained
SDRAM timing
register 2
DBTR2
H'0104 0303
Retained
Retained
SDRAM refresh DBRFCNT0
control register 0
H'0000 0000
Retained
Retained
SDRAM refresh DBRFCNT1
control register 1
H'0000 0200
Retained
Retained
SDRAM refresh DBRFCNT2
control register 2
H'1000 0080
Retained
Retained
SDRAM refresh DBRFSTS
status register
H'0000 0000
Retained
Retained
DDRPAD
DBFREQ
frequency setting
register
H'0000 0000
Retained
Retained
DDRPAD DIC, DBDICODTOCD
ODT, OCD setting
register
H'0000 0007
Retained
Retained
SDRAM mode
setting register
DBMRCNT
Undefined
Retained
Retained
Note: * Initial value is specified by external pin MODE8.
Rev.1.00 Jan. 10, 2008 Page 481 of 1658
REJ09B0261-0100