SH7785 Datasheet, PDF (825/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Mode
17.5.2 Releasing Deep Sleep Mode
Deep sleep mode is released by means of an interrupt (NMI, IRL, IRQ, GPIO, WDT interval
timer, or H-UDI) or a reset.
In deep sleep mode, an interrupt request is accepted even if the BL bit in SR is set to 1. The
SPC, SSR and other related contents should be saved before execute a SLEEP instruction if
necessary.
(1) Release by Interrupt
When an NMI, IRL, IRQ, GPIO, or WDT interval timer interrupt is generated, deep sleep mode is
released and the interrupt exception handling is executed. The code corresponding to the interrupt
source is set in INTEVT. For details of the timing of the changes in the STATUS pin, that is
similar to sleep mode, see section 17.7.2, Releasing Sleep Mode.
(2) Release by Reset
Deep sleep mode is released by means of a power-on via the PRESET pin or a WDT overflow, H-
UDI reset, or a manual reset by a WDT overflow. For details of the timing of the changes in the
STATUS pin, that is similar to sleep mode, see section 16.5, Status Pin Change Timing during
Reset.
Rev.1.00 Jan. 10, 2008 Page 795 of 1658
REJ09B0261-0100