SH7785 Datasheet, PDF (1099/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
21.3.13 Line Status Register n (SCLSR)
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ORER
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W*
Note: * Only 0 can be written to clear the flag.
Initial
Bit
Bit Name Value R/W Description
15 to 1 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ORER
0
R/W*¹ Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
0: Reception in progress, or reception has ended
normally*²
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ORER after reading ORER = 1,
1: An overrun error occurred during reception*³
[Setting condition]
• When the next serial reception is completed while
SCFRDR receives 64-byte data (SCFRDR is full)
Notes: 1. Only 0 can be written to clear the flag.
2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR
is cleared to 0.
3. The receive data prior to the overrun error is retained in SCFRDR, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
Rev.1.00 Jan. 10, 2008 Page 1069 of 1658
REJ09B0261-0100