SH7785 Datasheet, PDF (126/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Handling
5.4 Exception Types and Priorities
Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.3 Exceptions
Exception Execution
Category Mode
Exception
Reset
Abort type Power-on reset
Manual reset
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception
General
exception
Re-
execution
type
User break before instruction
execution*¹
Instruction address error
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
Slot illegal instruction exception
General FPU disable exception
Slot FPU disable exception
Data address error (read)
Data address error (write)
Data TLB miss exception (read)
Data TLB miss exception (write)
Data TLB protection
violation exception (read)
Data TLB protection
violation exception (write)
FPU exception
Initial page write exception
Exception Transition
Direction*³
Priority Priority Vector
Level*² Order*² Address
Offset
Exception
Code*⁴
1
1
H'A000 0000 —
H'000
1
2
H'A000 0000 —
H'020
1
1
H'A000 0000 —
H'000
1
3
H'A000 0000 —
H'140
1
4
H'A000 0000 —
H'140
2
0
(VBR/DBR) H'100/— H'1E0
2
1
(VBR)
H'100 H'0E0
2
2
(VBR)
H'400 H'040
2
3
(VBR)
H'100 H'0A0
2
4
(VBR)
H'100 H'180
2
4
(VBR)
H'100 H'1A0
2
4
(VBR)
H'100 H'800
2
4
(VBR)
H'100 H'820
2
5
(VBR)
H'100 H'0E0
2
5
(VBR)
H'100 H'100
2
6
(VBR)
H'400 H'040
2
6
(VBR)
H'400 H'060
2
7
(VBR)
H'100 H'0A0
2
7
(VBR)
H'100 H'0C0
2
8
(VBR)
H'100 H'120
2
9
(VBR)
H'100 H'080
Rev.1.00 Jan. 10, 2008 Page 96 of 1658
REJ09B0261-0100