SH7785 Datasheet, PDF (957/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Bit
10 to 8
Initial
Bit Name Value
CDEA 0
7
⎯
0
Internal
R/W Update Description
R/W None
CDE Output Timing Adjustment
000: Adjustment of output timing is not
performed.
The CDE signal is output at the rising edge
of the dot clock, with the reference timing.
001: The CDE signal is output at the rising edge,
delayed one dot clock cycle relative to the
reference timing.
010: The CDE signal is output at the rising edge,
delayed two dot clock cycles relative to the
reference timing.
011: The CDE signal is output at the rising edge,
delayed three dot clock cycles relative to
the reference timing.
100: The CDE signal is output at the falling
edge, preceding the reference timing by 1/2
dot clock cycle.
101: The CDE signal is output at the falling
edge, delayed 1/2 dot clock cycle relative to
the reference timing.
110: The CDE signal is output at the falling
edge, delayed (1+1/2) dot clock cycles
relative to the reference timing.
111: The CDE signal is output at the falling
edge, delayed (2+1/2) dot clock cycles
relative to the reference timing.
R
⎯
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 927 of 1658
REJ09B0261-0100