SH7785 Datasheet, PDF (1598/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
32.3.1 Clock and Control Signal Timing
Table 32.6 Clock and Control Signal Timing
Item
Symbol Min.
EXTAL clock Divider 1: × 1, PLL1: × 72, f_EX
12
input frequency PLL2 in operation*⁴
Divider 1: × 1, PLL1: × 36,
23
PLL2 in operation*⁶
EXTAL clock Divider 1: × 1, PLL1: × 72, t
59
EXcyc
input cycle time PLL2 in operation*⁴
Divider 1: × 1, PLL1: × 36,
29
PLL2 in operation*⁶
EXTAL clock input low pulse width
t_EXL
3.5
EXTAL clock input high pulse width
t_EXH
3.5
EXTAL clock input rise time
t
⎯
EXr
EXTAL clock input fall time
t
⎯
EXf
CLKOUT clock output (with use of PLL1/PLL2) f
25
OP
CLKOUT clock output cycle time
t
10
CKOcyc
CLKOUT clock output low pulse width
t
1
CKOL1
CLKOUT clock output high pulse width
t_CKOH1
1
CLKOUT clock output rise time
t_CKOr
⎯
CLKOUT clock output fall time
t_CKOf
⎯
CLKOUT clock output low pulse width
t_CKOL2
3
CLKOUT clock output high pulse width
t
3
CKOH2
Power-on oscillation settling time
t
10
OSC1
Power-on oscillation settling time/mode
(MODE14, MODE10, MODE9, MODE4 to
t
10
OSCMD
MODE0) settling time
MODE (MODE13 to MODE11, MODE8 to
t_MDRS
3
MODE5) reset setup time
Max.
17
34
83
43
⎯
⎯
4
4
101
1000
⎯
⎯
3
3
⎯
⎯
⎯
⎯
⎯
Unit Figure
MHz
ns 32.1
ns 32.1
ns 32.1
ns 32.1
ns 32.1
MHz
ns 32.2
ns 32.2
ns 32.2
ns 32.2
ns 32.2
ns 32.3
ns 32.3
ms 32.4
ms 32.4
t_cyc
32.6
Rev.1.00 Jan. 10, 2008 Page 1568 of 1658
REJ09B0261-0100