SH7785 Datasheet, PDF (322/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(9) Interrupt Mask Clear Register 1 (INTMSKCLR1)
INTMSKCLR1 is a 32-bit write-only register that clears the mask settings for the IRL interrupt
requests. Undefined values are read from this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC10 IC11 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Name
31
IC10
30
IC11
29 to 0 ⎯
Initial
Value
0
0
All 0
R/W Description
R/W Clears masking of IRL3 to [When read]
IRL0 interrupt sources
Undefined values are read.
when IRL3 to IRL0 operate
as an encoded interrupt
[When written]
input.
0: No effect
R/W Clears masking of IRL7 to ^{1: Clears the}
IRL4 interrupt sources
corresponding interrupt
when IRL7 to IRL4 operate ^{mask (enables the}
as an encoded interrupt
interrupt)
input.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 292 of 1658
REJ09B0261-0100