SH7785 Datasheet, PDF (639/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM)
This register is the mask register for PCIAINT.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
MBIM
TBT
OIM
MBT
OIM
—
—
—
—
—
—
—
TAIM MAIM
RDP
EIM
WDP
EIM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R/WC R/WC R/WC R R R R R R R R/WC R/WC R/WC R/WC
PCI R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 14 ⎯
13
MBIM
12
TBTOIM
11
MBTOIM
10 to 4 ⎯
3
TAIM
Initial
Value
All 0
0
0
0
All 0
0
R/W
Description
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
SH: R/WC Master-Broken Interrupt Mask
PCI: R
0: MBI disabled (masked)
1: MBI enabled (not masked)
SH: R/WC Target Bus Time-Out Interrupt Mask
PCI: R
0: TBTOI disabled (masked)
1: TBTOI enabled (not masked)
SH: R/WC Master Bus Time-Out Interrupt Mask
PCI: R
0: MBTOI disabled (masked)
1: MBTOI enabled (not masked)
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
SH: R/WC Target-Abort Interrupt Mask
PCI: R
0: TAI disabled (masked)
1: TAI enabled (not masked)
Rev.1.00 Jan. 10, 2008 Page 609 of 1658
REJ09B0261-0100