SH7785 Datasheet, PDF (49/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
No. Pin Name
217 BREQ/BSACK
218 BACK/BSREQ
219 DREQ0
220 DREQ1
221 DREQ2/INTB
222 DREQ3/INTC
223 DACK0
224 DACK1
225 DACK2/
SCIF2_TXD/
MMCCMD/
SIOF_TXD
226 DACK3/
SCIF2_SCK/
MMCDAT/
SIOF_SCK
227 DRAK2/CE2A
228 TCK
229 TMS
230 TDI
231 TDO
232 TRST
I/O
Function
I
Bus request (Master mode)/
Bus acknowledgement
(Slave mode)
O
Bus acknowledgement
(Master mode)/Bus request
(Slave mode)
I
DMA channel 0 request
I
DMA channel 1 request
I/I
DMA channel 2 request/PCI
interrupt B
I/I
DMA channel 3 request/PCI
interrupt C
O
DMA channel 0 bus
acknowledgment
O
DMA channel 1 bus
acknowledgment
O/O/O/I DMA channel 2 bus
O/O acknowledgment/SCIF2
transmit data/MMCIF
command response/SIOF
transmit data
O/O/IO/ DMA channel 3 bus
IO/IO acknowledgment/SCIF2
serial clock/MMCIF
data/SIOF serial clock
O/O DMA channel 2 transfer
request acknowledge
2/PCMCIA CE2A
I
H-UDI clock
I
H-UDI emulator
I
H-UDI data
O
H-UDI data
I
H-UDI emulator
No. Pin Name
233 ASEBRK/
BRKACK
234 AUDCK
I/O
Function
I
H-UDI emulator
O
H-UDI emulator clock
235 AUDSYNC
O
236 AUDATA0
O
237 AUDATA1
O
H-UDI emulator
H-UDI emulator data 0
H-UDI emulator data 1
238 AUDATA2
O
H-UDI emulator data 2
239 AUDATA3
O
H-UDI emulator data 3
240 SCIF0_TXD/
HSPI_TX/FWE
O/O/O
SCIF0 transmit data/HSPI
transmit data/NAND flash
write enable
241 SCIF0_RXD/ I/I/I
HSPI_RX/FRB
SCIF0 receive data/HSPI
receive data/NAND flash
ready or busy
242 SCIF0_SCK/ IO/IO/O SCIF0 serial clock/HSPI
HSPI_CLK/FRE
serial clock/NAND flash read
enable
243 SCIF0_RTS/
HSPI_CS/FSE
IO/IO/O SCIF0 modem control/HSPI
chip selection/NAND flash
spare area enable
244 SCIF0_CTS/
INTD/FCE
IO/I/O
SCIF0 modem control/PCI
interrupt D/NAND flash chip
enable
245 SCIF1_TXD
O
SCIF1 transmit data
246 SCIF1_RXD I
SCIF1 receive data
247 SCIF1_SCK IO
SCIF1 serial clock
248 SCIF2_RXD/ I/I
SIOF_RXD
SCIF2 receive data/SIOF
receive data
Rev.1.00 Jan. 10, 2008 Page 19 of 1658
REJ09B0261-0100