SH7785 Datasheet, PDF (1297/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. Audio Codec Interface (HAC)
Table 25.2 Register Configuration (2)
Channel Register Name Abbrev.
Power-on
Reset by
PRESET
Pin/WDT/
H-UDI
Manual
Reset by
WDT/
Multiple
Exceptions
Sleep by
Sleep
Instruction
Module
Standby
0
Control and status HACCR0 H'0000 0200 H'0000 0200 Retained Retained
register 0
0
Command/status HACCSAR0 H'0000 0000 H'0000 0000 Retained Retained
address register 0
0
Command/status HACCSDR0 H'0000 0000 H'0000 0000 Retained Retained
data register 0
0
PCM left channel HACPCML0 H'0000 0000 H'0000 0000 Retained Retained
register 0
0
PCM right channel HACPCMR0 H'0000 0000 H'0000 0000 Retained Retained
register 0
0
TX interrupt enable HACTIER0 H'0000 0000 H'0000 0000 Retained Retained
register 0
0
TX status register HACTSR0 H'F000 0000 H'F000 0000 Retained Retained
0
0
RX interrupt
HACRIER0 H'0000 0000 H'0000 0000 Retained Retained
enable register 0
0
RX status register HACRSR0 H'0000 0000 H'0000 0000 Retained Retained
0
0
HAC control
HACACR0 H'8400 0000 H'8400 0000 Retained Retained
register 0
Deep
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev.1.00 Jan. 10, 2008 Page 1267 of 1658
REJ09B0261-0100