SH7785 Datasheet, PDF (776/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
19
BFST3
x
18
BFST2
x
17
BFST1
x
16
BFST0
1
R
Frequency division ratio of the bus clock (Bck)
R
0101: × 1/12
R
0110: × 1/16
R
0111: × 1/18
1000: × 1/24
1001: × 1/32
1010: × 1/36
1011: × 1/48
15
MFST3
0
14
MFST2
0
13
MFST1
1
12
MFST0
x
R
Frequency division ratio of the DDR clock (DDRck)
R
0010: ×1/4
R
0011: ×1/6
R
11
S2FST3 0
10
S2FST2 1
9
S2FST1 0
8
S2FST0 x
R
Frequency division ratio of the GDTA clock (GAck)
R
0100: × 1/8
R
0101: × 1/12
R
1111: Stop the clock supply.
7
S3FST3 x
R
Frequency division ratio of the DU clock (DUck)
6
S3FST3 1
R
0100: × 1/8
5
S3FST3 x
R
0101: × 1/12
4
S3FST3 x
R
0110: × 1/16
0111: × 1/18
1000: × 1/24
1001: × 1/32
1010: × 1/36
1011: × 1/48
1111: Stop the clock supply
3
PFST3
1
R
Frequency division ratio of the peripheral clock (Pck)
2
PFST2
0
R
0111: × 1/18
1
PFST1
x
R
1000: × 1/24
0
PFST0
x
R
1001: × 1/32
1010: × 1/36
1011: × 1/48
Rev.1.00 Jan. 10, 2008 Page 746 of 1658
REJ09B0261-0100