SH7785 Datasheet, PDF (1093/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5
TTRG1 0
4
TTRG0 0
3
MCE*¹
0
R/W Transmit FIFO Data Count Trigger
R/W These bits are used to set the number of remaining
transmit data bytes that sets the TDFE flag in SCFSR.
The TDFE flag is set when the number of transmit data
bytes in SCFTDR is equal to or less than the trigger
setting count shown below.
00: 32 (32)*²
01:16 (48)
10: 2 (62)
11: 0 (64)
R/W Modem Control Enable
Enables the SCIF_CTS and SCIF_RTS modem control
signals. Always set the MCE bit to 0 in clocked
synchronous mode.
0: Modem signals disabled*³
1: Modem signals enabled
2
TFCL
0
R/W Transmit FIFO Data Count Register Clear
Clears the transmit data count in the transmit FIFO
data count register to 0.
0: The FIFO data count not cleared*⁴
1: The FIFO data count cleared to 0
1
RFCL
0
R/W Receive FIFO Data Count Register Clear
Clears the receive data count in the receive FIFO data
count register to 0.
0: The FIFO data count not cleared*⁴
1: The FIFO data count cleared
0
LOOP
0
R/W Loopback Test
Internally connects the transmit output pin (SCIF_TXD)
and receive input pin (SCIF_RXD), and the SCIF_RTS
pin and SCIF_CTS pin, enabling loopback testing.
0: Loopback test disabled
1: Loopback test enabled
Notes: 1. Only channel 0. Reserved bit in channels 1 to 5.
2. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set.
3. SCIF_CTS is fixed at active-0 regardless of the input value, and SCIF_RTS output is
also fixed at 0.
4. A reset operation is performed in the event of a power-on reset or manual reset.
Rev.1.00 Jan. 10, 2008 Page 1063 of 1658
REJ09B0261-0100