SH7785 Datasheet, PDF (653/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(23) PCI I/O Bank Mask Register (PCIIOBMR)
This register is the mask register for PCIIOBR. This register specifies the I/O space size on the
PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC.
See section 13.4.3 (3), Accessing PCI I/O Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———————————
IOBAM
——
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit
Bit Name
31 to 21 —
Initial
Value
All 0
R/W
SH: R
PCI: ⎯
20 to 18 IOBAM
All 0 SH: R/W
PCI: ⎯
17 to 0 ⎯
All 0 SH: R
PCI: ⎯
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI I/O Space Bank Address Mask (3 bits)
000: 256 kbytes
001: 512 kbytes
011: 1 Mbyte
111: 2 Mbytes
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 623 of 1658
REJ09B0261-0100