SH7785 Datasheet, PDF (1079/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5
PE
0
4
O/E
0
R/W Parity Enable
In asynchronous mode, selects whether or not parity bit
addition is performed in transmission, and parity bit
checking is performed in reception.
In clocked synchronous mode, parity bit addition and
checking is disabled regardless of the PE bit setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*¹
R/W Parity Mode
Selects either even or odd parity for use in parity
addition and checking. In asynchronous mode, the O/E
bit setting is only valid when the PE bit is set to 1,
enabling parity bit addition and checking. In clocked
synchronous mode or when parity addition and
checking is disabled in asynchronous mode, the O/E bit
setting is invalid.
0: Even parity
1: Odd parity
When even parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is even. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is even.
When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1-bits in the
transmit character plus the parity bit is odd. In
reception, a check is performed to see if the total
number of 1-bits in the receive character plus the parity
bit is odd.
Rev.1.00 Jan. 10, 2008 Page 1049 of 1658
REJ09B0261-0100