SH7785 Datasheet, PDF (879/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.3 Display Status Register (DSSR)
The display status register (DSSR) is a register used to read, from outside, the internal state of the
display unit (DU).
Bit: 31 30 29
———
Initial value: 0
0
1
R/W: R R R
Internal update:
Bit: 15 14 13
TVR FRM —
Initial value: 0
0
0
R/W: R R R
Internal update:
28 27 26 25 24 23
——————
1
0
0
0
0
0
RRRRRR
12 11 10 9
8
7
— VBK — RINT HBK —
0
0
0
0
0
0
RRRRRR
22 21 20 19 18 17 16
— DFB6 DFB5 DFB4 DFB3 DFB2 DFB1
0
0
0
0
0
0
0
RRRRRRR
6
5
4
3
2
1
0
———————
0
0
0
0
0
0
0
RRRRRRR
Bit
31, 30
Bit Name
⎯
Initial
Value
00
29, 28 ⎯
11
27 to 22 ⎯
All 0
21
DFB6
0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R
⎯
Reserved
These bits are always read as 1. The write value
should always be 1.
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R
None Display Frame Buffer 6 Flag
0: The address indicated by the plane 6 display
area start address 0 register (P6DSA0R) in
plane 6 is being used as the display area start
address
1: The address indicated by the plane 6 display
area start address 1 register (P6DSA1R) in
plane 6 is being used as the display area start
address
Rev.1.00 Jan. 10, 2008 Page 849 of 1658
REJ09B0261-0100