SH7785 Datasheet, PDF (901/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.16 Vertical Sync Point Register (VSPR)
The vertical sync point register (VSPR) sets the start position of the vertical sync signal in raster
line units. The value is retained during power-on reset and manual reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
——————
VSP
Initial value: 0
0
0
0
0
0 ——————————
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Internal update:
OOOOOOOOOO
Initial
Bit
Bit Name Value R/W
31 to 10 ⎯
All 0
R
9 to 0 VSP
Undefined R/W
Internal
Update Description
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Yes
Vertical Sync Point
The start position of the vertical sync signal
should be set in raster line units.
When in TV sync mode, this register should be
set such that the VSYNC falling edge set
position in this register is the same as or later
than the EXVSYNC falling edge.
Rev.1.00 Jan. 10, 2008 Page 871 of 1658
REJ09B0261-0100