SH7785 Datasheet, PDF (127/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Handling
Exception Transition
Direction*³
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level*² Order*² Address
Offset
Exception
Code*⁴
General Completion Unconditional trap (TRAPA) 2
exception type
User break after instruction
2
execution*
Interrupt Completion Nonmaskable interrupt
3
type
General interrupt request
4
4
(VBR)
H'100
H'160
10
(VBR/DBR) H'100/— H'1E0
—
(VBR)
H'600
H'1C0
—
(VBR)
H'600
—
Notes: 1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100.
2. Priority is first assigned by priority level, then by priority order within each level (the
lowest number represents the highest priority).
3. Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases.
4. Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
Rev.1.00 Jan. 10, 2008 Page 97 of 1658
REJ09B0261-0100