SH7785 Datasheet, PDF (1271/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
• An error in a command sequence (during data reception) is detected through the CRC error
flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1,
issue CMD12 and suspend the command sequence.
• The data remains in FIFO after the read sequence end. Set the SET[2:0] bits in DMACR to 100
to read all data in FIFO if necessary.
• Confirm the DMA transfer end and clear the DMAEN bit in DMACR to 0.
• Set the CMDOFF bit to 1 and clear DMACR to H'00 if a CRC error (CRCERI) or a command
timeout error (CTERI) occurs in the command response reception.
• Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO if a CRC error (CRCERI) or
a data timeout error (DTERI) occurs in the read data reception.
Notes: 1. In multiple block transfer, when the command sequence is ended (the CMDOFF bit is
written to 1) before command response reception (CRPI), the command response may
not be received correctly. Therefore, to receive the command response correctly, the
command sequence must be continued (set the RD_CONT bit to 1) until the command
response reception ends.
2. Access from the DMAC to FIFO must be done in bytes or words.
Rev.1.00 Jan. 10, 2008 Page 1241 of 1658
REJ09B0261-0100