SH7785 Datasheet, PDF (1405/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
Start of command access (flash read)
Common control register (FLCMNCR)
ACM[1:0] = B'00 (command access mode)
CE0 = B'1 (enable the chip)
TYPESEL = B'1 (select NAND-type flash memory)
Command control register (FLCMDCR)
DOCMD1 = B'1 (execute first command stage)
DOADR = B'1 (execute address stage)
ADRMD = B'1 (address register value is output as
memory address)
ADRCNT[1:0] = B'10 (issue 3-byte address)
DOSR = B'1 (perform status read)
Command code register (FLCMCDR)
CMD[7:0] = H'00 (flash read command)
Address register (FLADR)
Set addresses to ADR[7:0], ADR[15:8], and ADR[23:16]
Data counter register (FLDTCNTR)
Specify number of bytes of read data to DTCNT[11:0]
Interrupt DMA control register (FLINTDMACR)
Set enable bit of DMA transfer or interrupt request to 1
Transfer control register (FLTRCR)
TRSTRT = B'1 (start flash memory access)
Perform flash memory reading
Issue first command
Issue address
Issue second command
Read status
FLTRCR.TREND = B'1?
No
Yes
End of flash memory access
FLTRCR.TREND = B'0 (clear processing end flag)
Read status
Check FLBSYCNT.STAT[7:0]
End of command access (flash read)
Figure 27.13 NAND Command Access (Flash Read)
Rev.1.00 Jan. 10, 2008 Page 1375 of 1658
REJ09B0261-0100