SH7785 Datasheet, PDF (1007/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
Table 20.4 GDTA Register States in Each Processing Mode (GDTA Common Registers)
Register
Abbreviation
GACMR
GACER
GACISR
GACICR
GACIER
DWCL_CTL
DRCL_CTL
DRMC_CTL
DWMC_CTL
DCP_CTL
DID_CTL
Power-On Reset Manual Reset
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Deep Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Table 20.5 GDTA States in Each Processing Mode (CL Block)
Register
Abbreviation
Power-On Reset Manual Reset
CLCF
H'0000 0000
H'0000 0000
CLCR
H'0000 0000
H'0000 0000
CLSR
H'0000 0000
H'0000 0000
CLWR
H'0000 0000
H'0000 0000
CLHR
H'0000 0000
H'0000 0000
CLIYPR
H'0000 0000
H'0000 0000
CLIUVPR
H'0000 0000
H'0000 0000
CLOPR
H'0000 0000
H'0000 0000
CLPLPR
H'0000 0000
H'0000 0000
Note: A 0 is always read from these registers.
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Deep Sleep
H'0000_0000
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev.1.00 Jan. 10, 2008 Page 977 of 1658
REJ09B0261-0100