SH7785 Datasheet, PDF (596/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(4) PCI Status Register (PCISTATUS)
PCISTATUS is used to record status information for events related to the PCI bus. The reserved
bits are read-only bits that are read as 0.
Reading from this register is normally performed. During writing, the write clear bit can be reset,
but it cannot be set (R/WC in the figure below). Write 1 to the bit to be cleared. For example, to
clear bit 14 so that other bits will not be affected, write the B'0100 0000 0000 0000 to this register.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DPE SSE RMA RTA STA
DEVSEL MDPE FBBC ⎯ 66C CL
⎯
⎯
⎯
⎯
Initial value: 0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
SH R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC R R R/W R R R R R
PCI R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC R R R R R R R R
Initial
Bit
Bit Name Value R/W
Description
15
DPE
0
SH: R/WC Parity Error Detect Status
PCI: R/WC Indicates that a parity error was detected in read data
when the PCIC is a master, or in write data when the
PCIC is a target. This bit is set regardless of the value
of parity error response bit.
0: Device did not detect parity error.
1: Device detected parity error.
14
SSE
0
SH: R/WC System Error Output Status
PCI: R/WC Indicates that the PCIC asserted SERR.
0: SERR was asserted
1: SERR was asserted (the value is retained until this
bit is cleared)
13
RMA
0
SH: R/WC Master Abort Receive Status
PCI: R/WC This bit indicates that a transaction was completed by
master abort when the PCIC is a master.
0: Transaction is not completed by master abort
1: The bus master detected completion of transaction
by master abort. Master abort is not set in special
cycles.
Rev.1.00 Jan. 10, 2008 Page 566 of 1658
REJ09B0261-0100