SH7785 Datasheet, PDF (1030/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.21 MC Command FIFO (MCCF)
MCCF is in the MC register block and receives commands. This register uses the FIFO method
and recognizes a maximum of eight command parameters according to the writing order. This
register does not retain the written values. This register is always read as 0.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MC_CF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MC_CF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Bit
Bit Name
31 to 0 MC_CF
Initial
Value R/W Description
0
W Command FIFO Register
Setting Method: When accessing this register, the MC_EN bit in GACER should be set to 1.
Access is possible only when the MC_EN bit is set to 1. If the MC_EN bit is 0, access is invalid
(writing is invalid; the read value is indefinite).
The following shows the setting contents assumed according to the writing order:
Rev.1.00 Jan. 10, 2008 Page 1000 of 1658
REJ09B0261-0100