SH7785 Datasheet, PDF (1120/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
(5) Serial Data Reception (Clocked Synchronous Mode)
Figure 21.19 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags
are cleared to 0.
Initialization
Start of reception
Read ORER flag in SCLSR
[1]
[1] SCIF initialization:
See Sample SCIF Initialization Flowchart in figure
21.16.
[2] Receive error handling:
Read the ORER flag in SCLSR to identify any error,
perform the appropriate error handling, then clear the
ORER flag to 0.
Transmission/reception cannot be resumed while the
ORER flag is set to 1.
ORER = 1 ?
Yes
[3] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, and clear the RDF flag to
[2]
0. The transition of the RDF flag from 0 to 1 can also
be identified by an RXI interrupt.
No
Error handling
[4] Serial reception continuation procedure:
Read RDF flag in SCFSR
[3]
To continue serial reception, read at east the receive
trigger setting count of receive data bytes from
SCFRDR, read 1 from the RDF flag, then clear the
No
RDF = 1 ?
RDF flag to 0. The number of receive data bytes in
SCFRDR can be ascertained by reading SCRFDR.
Yes
Read receive data in SCFRDR, and
[4]
clear RDF flag in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 21.19 Sample Serial Reception Flowchart (1)
Rev.1.00 Jan. 10, 2008 Page 1090 of 1658
REJ09B0261-0100