SH7785 Datasheet, PDF (777/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
15.4.4 PLL Control Register (PLLCR)
PLLCR is a 32-bit readable/writable register that controls the clock output on the CLKOUT pin.
This register can only be accessed in longwords.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CKOFF ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R
Initial
Bit
Bit Name Value R/W
31 to 24 ⎯
0
R
23 to 16 ⎯
All 0 R/W
15 to 2 ⎯
All 0 R
1
CKOFF 0
R/W
0
⎯
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 0. The write value
should always be 0. If a value other than 0 is written,
the operation is not guaranteed.
Reserved
These bits are always read as 0. The write value
should always be 0.
CLKOUT Output Enabled
Stops clock output on the CLKOUT pin
0: Clock is output on the CLKOUT pin
1: The CLKOUT pin is placed in the high impedance
state
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 747 of 1658
REJ09B0261-0100