SH7785 Datasheet, PDF (205/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
VA is
in P4 area
Data access to virtual address (VA)
VA is
in P2 area
VA is
in P1 area
0
CCR.OCE?
1
1
CCR.CB?
0
0
CCR.OCE?
1
0
CCR.WT?
1
Data TLB miss
exception
No
VPNs match
and V = 1
Yes
Data TLB multiple
hit exception
0 (User)
VA is in P0, U0,
or P3 area
MMUCR.AT = 1
No
Yes
SH = 0
No _{and (MMUCR.SV = 0 or}
SR.MD = 0)
Yes
No
VPNs match,
ASIDs match, and
V=1
Yes
No
Only one
entry matches
Yes
SR.MD?
1 (Privileged)
R/W?
R
0 _EPR[2]?
1
W
0 _EPR[1]?
1
Data TLB protection
violation exception
W
EPR[4]?
1
R/W?
0
0
D?
1
Initial page write
exception
R
EPR[5]? ⁰
1
Data TLB protection
violation exception
No
C = 1 and
CCR.OCE = 1
Yes
0
WT?
1
Internal resource access
Memory access
(Non-cacheable)
Cache access
in copy-back mode
Cache access
in write-through mode
Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode)
Rev.1.00 Jan. 10, 2008 Page 175 of 1658
REJ09B0261-0100