SH7785 Datasheet, PDF (883/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.4 Display Unit Status Register Clear Register (DSRCR)
The display unit status register clear register (DSRCR) is a register which clears the various flags
in DSSR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TVCL FRCL — — VBCL — RICL HBCL — — — — — — — —
Initial value: — — 0
0 — 0 —— 0
0
0
0
0
0
0
0
R/W: W W R R W R W W R R R R R R R R
Internal update:
Initial
Bit
Bit Name Value R/W
31 to 16 ⎯
All 0
R
15
TVCL Undefined W
14
FRCL Undefined W
13, 12 ⎯
All 0
R
11
VBCL Undefined W
10
⎯
0
R
Internal
Update Description
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
None
TV Synchronous Signal Error Flag Clear
0: The TVR flag in DSSR is not changed.
1: The TVR flag in DSSR is cleared to 0.
None
Flame Flag Clear
0: The FRM flag in DSSR is not changed.
1: The FRM flag in DSSR is cleared to 0.
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
None
Vertical Blanking Flag Clear
0: The VBK flag in DSSR is not changed.
1: The VBK flag in DSSR is cleared to 0.
⎯
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 853 of 1658
REJ09B0261-0100