SH7785 Datasheet, PDF (241/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Caches
8. Caches
This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte
operand cache (OC) for data.
8.1 Features
The features of the cache are given in table 8.1.
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. The features of the store queues are given in table 8.2.
Table 8.1 Cache Features
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Instruction Cache
Operand Cache
32-Kbyte cache
32-Kbyte cache
4-way set-associative, virtual
4-way set-associative, virtual
address index/physical address tag address index/physical address tag
32 bytes
32 bytes
256 entries/way
256 entries/way
⎯
Copy-back/write-through selectable
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Table 8.2 Store Queue Features
Item
Capacity
Addresses
Write
Write-back
Access right
Store Queues
32 bytes × 2
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
When MMU is disabled: Determined by SQMD bit in MMUCR
When MMU is enabled: Determined by PR for each page
The operand cache of this LSI is 4-way set associative, each may comprising 256 cache lines.
Figure 8.1 shows the configuration of the operand cache.
The instruction cache is 4-way set-associative, each way comprising 256 cache lines. Figure 8.2
shows the configuration of the instruction cache.
Rev.1.00 Jan. 10, 2008 Page 211 of 1658
REJ09B0261-0100