SH7785 Datasheet, PDF (399/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W
19, 18 ⎯
All 0 R
17
BREQEN 0
R/W
16
DMABST 0
R/W
15
⎯
0
R
14
HIZCNT 0
R/W
13 to 7 ⎯
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
BREQ Enable
Specifies whether an external request can be accepted
or not. In the initialized state at a power-on reset, an
external request is not accepted. When this LSI is
booted up in slave mode, an external request is
accepted regardless of the BREQEN value.
0: An external request is not accepted
1: An external request is accepted
DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by DMA
channels 0 to 5. When this bit is cleared to 0, the
priority is as follows: bus release, DMAC (burst mode),
CPU, DMAC, PCIC. When this bit is set to 1, the bus is
not released until completion of the DMAC burst
transfer. This bit is initialized at a power-on reset.
0: DMAC burst mode transfer priority setting is off
1: DMAC burst mode transfer priority setting is on
Reserved
This bit is always read as 0. The write value should
always be 0.
High Impedance (Hi-Z) Control
Specifies the state of signals WEn and RD/FRAME in
the bus-released state.
0: Signals WEn and RD/FRAME are high-impedance in
the bus-released state
1: Signals WEn and RD/FRAME are driven in the bus-
released state
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 369 of 1658
REJ09B0261-0100