SH7785 Datasheet, PDF (92/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Instruction Set
Instruction
SYNCO
TRAPA #imm
Operation
Instruction Code
Data accesses invoked
by the following
instructions are not
executed until execution
of data accesses which
precede this instruction
has been completed.
0000000010101011
PC + 2 → SPC,
11000011iiiiiiii
SR → SSR, R15 → SGR,
1 → SR.MD/BL/RB, #imm
<< 2 → TRA,
H'160 → EXPEVT,
VBR + H'0100 → PC
Privileged T Bit New
⎯
⎯ New
—
——
Table 3.10 Floating-Point Single-Precision Instructions
Instruction
Operation
Instruction Code Privileged T Bit
FLDI0
FRn
H'0000 0000 → FRn
1111nnnn10001101 —
—
FLDI1
FRn
H'3F80 0000 → FRn
1111nnnn10011101 —
—
FMOV
FRm,FRn
FRm → FRn
1111nnnnmmmm1100 —
—
FMOV.S @Rm,FRn
(Rm) → FRn
1111nnnnmmmm1000 —
—
FMOV.S @(R0,Rm),FRn (R0 + Rm) → FRn
1111nnnnmmmm0110 —
—
FMOV.S @Rm+,FRn (Rm) → FRn, Rm + 4 → Rm 1111nnnnmmmm1001 —
—
FMOV.S FRm,@Rn
FRm → (Rn)
1111nnnnmmmm1010 —
—
FMOV.S FRm,@-Rn
Rn-4 → Rn, FRm → (Rn) 1111nnnnmmmm1011 —
—
FMOV.S FRm,@(R0,Rn) FRm → (R0 + Rn)
1111nnnnmmmm0111 —
—
FMOV
DRm,DRn
DRm → DRn
1111nnn0mmm01100 —
—
FMOV
@Rm,DRn
(Rm) → DRn
1111nnn0mmmm1000 —
—
FMOV
@(R0,Rm),DRn (R0 + Rm) → DRn
1111nnn0mmmm0110 —
—
FMOV
@Rm+,DRn (Rm) → DRn, Rm + 8 → Rm 1111nnn0mmmm1001 —
—
FMOV
DRm,@Rn
DRm → (Rn)
1111nnnnmmm01010 —
—
FMOV
DRm,@-Rn Rn-8 → Rn, DRm → (Rn) 1111nnnnmmm01011 —
—
FMOV
DRm,@(R0,Rn) DRm → (R0 + Rn)
1111nnnnmmm00111 —
—
FLDS
FRm,FPUL
FRm → FPUL
1111mmmm00011101 —
—
FSTS
FPUL,FRn
FPUL → FRn
1111nnnn00001101 —
—
FABS
FRn
FRn & H'7FFF FFFF → FRn 1111nnnn01011101 —
—
New
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Rev.1.00 Jan. 10, 2008 Page 62 of 1658
REJ09B0261-0100