SH7785 Datasheet, PDF (330/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
3. Branch to the device driver.
4. In the device driver operating in user mode, set the UIMASK bits to mask the B-type
interrupts.
5. Process more urgent interrupts in the device driver.
6. Clear the UIMASK bit to 0 and return from the processing by the device driver.
10.3.3 On-chip Module Interrupt Priority Registers
(1) Interrupt Priority Registers (INT2PRI0 to INT2PRI9)
INT2PRI0 to INT2PRI9 are 32-bit readable/writable registers that set priority levels (31 to 0) of
the on-chip peripheral module interrupts. These registers are initialized to H'0000 0000 by a reset.
These registers can set the priority of each interrupt source in 30 levels (H'00 and H'01 mask the
interrupt request) by the 5-bit field.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯
⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯
⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Table 10.5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to
INT2PRI9.
Rev.1.00 Jan. 10, 2008 Page 300 of 1658
REJ09B0261-0100