SH7785 Datasheet, PDF (884/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Bit
9
8
7 to 0
Initial
Bit Name Value R/W
RICL
Undefined W
HBCL Undefined W
⎯
All 0
R
Internal
Update Description
None
Vertical Blanking Flag Clear
0: The RINT flag in DSSR is not changed.
1: The RINT flag in DSSR is cleared to 0.
None Vertical Blanking Flag Clear
0: The HBK flag in DSSR is not changed.
1: The HBK flag in DSSR is cleared to 0.
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
19.3.5 Display Unit Interrupt Enable Register (DIER)
The display unit interrupt enable register (DIER) is a register which enables interrupts to the CPU
the causes of which are internal states of the display unit (DU) reflected in DSSR. When bits are
set in this register, if bits in the same bit positions in DSSR are set, an interrupt is issued to the
CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TVE FRE — — VBE — RIE HBE — — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R/W R R/W R/W R R R R R R R R
Internal update:
Rev.1.00 Jan. 10, 2008 Page 854 of 1658
REJ09B0261-0100