SH7785 Datasheet, PDF (1121/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 21.19 Sample Serial Reception Flowchart (2)
In serial reception, the SCIF operates as follows.
1. The SCIF is initialized internally in synchronization with the input or output of the
synchronization clock.
2. The receive data is stored in SCRSR in LSB-to-MSB order.
After receiving the data, the SCIF checks whether the receive data can be transferred from
SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an
overrun error is detected in the error check, reception cannot continue.
3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
interrupt (RXI) request is generated.
If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI)
request is generated.
Figure 21.20 shows an example of the SCIF reception operation.
Rev.1.00 Jan. 10, 2008 Page 1091 of 1658
REJ09B0261-0100