SH7785 Datasheet, PDF (568/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
MCK0,
MCK1
MCKE
High level
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
Valid Invalid Valid Valid Invalid Valid Invalid Valid
Invalid
MA[10]
Valid Invalid Valid Valid Invalid Valid Invalid Valid Invalid
Invalid
Valid Invalid
Valid Invalid
MBA[2:0] Valid Invalid Valid Valid Invalid Valid Invalid Valid Invalid Valid Invalid Valid Invalid
Example of CL = 3
tRRD
= 2 cycles
tRTP
= 2 cycles
MDQS[3:0]
MDM[3:0]
Invalid
MDQ[31:0]
SDRAM _ACT
command _{bank A}
Invalid
ACT READ
bank B bank A
READ
bank B
Read data
READ
bank C
PRE
bank C
Figure 12.15 tRRD and tRTP
Invalid
ACT
bank C
Figure 12.15 shows a case in which the pages for both of banks A and B are closed, the page for
bank C is open, and a page hit has occurred. When the tRRD time constraint has been satisfied
starting from issue of the ACT command for bank A, the ACT command for bank B is issued.
Because time tRCD has elapsed from the issue of the ACT command for bank A, a READ
command can be used. The READ command has a burst length of 4, so after two cycles a READ
command for bank B can be issued. A further two cycles later, a READ command for bank C can
be issued. However, the next request is access for which bank C must be closed, and so after the
elapse of time tRTP a PRE command is issued.
Rev.1.00 Jan. 10, 2008 Page 538 of 1658
REJ09B0261-0100