SH7785 Datasheet, PDF (601/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(8) PCI Base Class Code Register (PCIBCC)
This field defines the base class code. For details of the class code, see appendix D in PCI Local
Bus Specification Revision 2.2.
Bit: 7
6
5
4
3
2
1
0
BCC
Initial value: x
x
x
x
x
x
x
x
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: R R R R R R R R
Bit
7 to 0
Bit Name
BCC
Initial
Value
H'xx
R/W
SH: R/W
PCI: R
Description
Base Class Code
These bits indicate the base class code. The initial
value is H'xx.
(9) PCI Cache Line Size Register (PCICLS)
Bit: 7
6
5
4
3
2
1
0
CLS
Initial value: 0
0
1
0
0
0
0
0
SH R/W: R R R R R R R R
PCI R/W: R R R R R R R R
Bit
7 to 0
Bit Name
CLS
Initial
Value
H'20
R/W
SH: R
PCI: R
Description
Cache Line Size
SBO and SDON are ignored because a memory
target does not support cache.
Rev.1.00 Jan. 10, 2008 Page 571 of 1658
REJ09B0261-0100