SH7785 Datasheet, PDF (1191/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23. Serial Peripheral Interface (HSPI)
23.3.3 System Control Register (SPSCR)
SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode,
selects either LSB first or MSB first in transmitting/receiving data, and master or slave mode.
If any of the FFEN, LMSB, CSA, or MASL bit values are changed, the module will undergo a
software reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15
—
Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— TEIE THIE RNIE RHIE RFIE FFEN LMSB CSV CSA TFIE ROIE RXDE TXDE MASL
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 14 ⎯
Initial
Value
All 0
13
TEIE
0
12
THIE
0
11
RNIE
0
10
RHIE
0
9
RFIE
0
R/W Description
R
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
R/W Transmit FIFO Empty Interrupt Enable
0: Transmit FIFO empty interrupt disabled
1: Transmit FIFO empty interrupt enabled
R/W Transmit FIFO Halfway Interrupt Enable
0: Transmit FIFO halfway interrupt disabled
1: Transmit FIFO halfway interrupt enabled
R/W Receive FIFO Not Empty Interrupt Enable
0: Receive FIFO not empty interrupt disabled
1: Receive FIFO not empty interrupt enabled
R/W Receive FIFO Halfway Interrupt Enable
0: Receive FIFO halfway interrupt disabled
1: Receive FIFO halfway interrupt enabled
R/W Receive FIFO Full Interrupt Enable
0: Receive FIFO full interrupt disabled
1: Receive FIFO full interrupt enabled
Rev.1.00 Jan. 10, 2008 Page 1161 of 1658
REJ09B0261-0100