SH7785 Datasheet, PDF (1379/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
27.3.4 Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies an address to be output in command
access mode. In sector access mode, a physical sector number specified in the physical sector
address bits is converted into an address to be output.
• Command access mode
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADR[31:24]
ADR[23:16]
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ADR[15:8]
ADR[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 24 ADR[31:24] H'00 R/W
23 to 16 ADR[23:16] H'00 R/W
15 to 8 ADR[15:8] H'00 R/W
7 to 0 ADR[7:0] H'00 R/W
Description
Fourth Address Data
Specify the fourth data to be output to flash memory as
an address in command access mode.
Third Address Data
Specify the third data to be output to flash memory as
an address in command access mode.
Second Address Data
Specify the second data to be output to flash memory
as an address in command access mode.
First Address Data
Specify the first data to be output to flash memory as an
address in command access mode.
Rev.1.00 Jan. 10, 2008 Page 1349 of 1658
REJ09B0261-0100