SH7785 Datasheet, PDF (102/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Pipelining
(5-1) LDS to MACH/L: 1 issue cycle
I1
I2
I3
ID s1
s2
s3 WB
MS
(5-2) LDS.L to MACH/L: 1 issue cycle
I1
I2
I3
ID
S1
S2
S3 WB
MS
(5-3) STS from MACH/L: 1 issue cycle
I1
I2
I3
ID s1
s2
s3 WB
MS
(5-4) STS.L from MACH/L: 1 issue cycle
I1
I2
I3
ID
S1
S2
S3 WB
MS
(5-5) MULS.W, MULU.W: 1 issue cycle
I1
I2
I3
ID E1
M2 M3 MS
(5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle
I1
I2
I3
ID E1 M2 M3
M2 M3 MS
(5-7) CLRMAC: 1 issue cycle
I1
I2
I3
ID E1
M2 M3 MS
(5-8) MAC.W: 2 issue cycle
I1
I2
I3
ID
S1
S2
S3 WB
ID
S1 S2 S3 WB
M2 M3 MS
(5-9) MAC.L: 2 issue cycle
I1
I2
I3
ID
S1
S2
S3 WB
ID
S1 S2 S3 WB
M2 M3
M2 M3 MS
Figure 4.2 Instruction Execution Patterns (6)
Rev.1.00 Jan. 10, 2008 Page 72 of 1658
REJ09B0261-0100