SH7785 Datasheet, PDF (797/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.3.4 Watchdog Timer Counter (WDTCNT)
WDTCNT is a 32-bit read-only register comprising a 12-bit counter that is incremented by the
WDTBCNT overflow signal. When WDTCNT overflows, a reset of the selected type is initiated
in watchdog timer mode, or an interrupt is generated in interval timer mode.
WDTCNT is only reset by a power-on reset. Writing to this register is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯
WDTCNT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W
31 to 12 ⎯
All 0 R
11 to 0 WDTCNT All 0 R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Counter value
Rev.1.00 Jan. 10, 2008 Page 767 of 1658
REJ09B0261-0100